v0.11.3 - Now backends will automaticaly merge combinatorial process if they share some conditional scope - Add xx.noBackendCombMerge feature to avoid the above feature on a specific signal - BusSlaveFactory rework primitives to allow ranged access and bus halt request for multicycles registers - remove automatic keywords from functions emited into the verilog backend - Fix default feature when used on outputs - More AXI4 fancy convertions functions - Add noBackendCombMerge feature - Add noCombLoopCheck syntax - addGeneric syntax added for blackboxes - Fix axi driveAx region default value - Better quartus/vivado flow