v0.11.4 - Add BitVector.resize(8 bits) syntax - Remove BitVector.apply(Int,Int) in favor of BitVector.apply(Int downto Int) - Vec.apply(UInt) is now emited with dedicated process + switch statement by backends instead of a 2->1 mux tree - Verilog backend now use always@(*) instead of always@(a,b,c, ...) - Rework BusSlaveFactory to allow multicycle registers access and to map memories - restore onlyStdLogicVectorAtTopLevelIo feature - Fix Vec(Vec(in/out/master/slave/Reg(x))) - Others lib fixes