FSM StateDelay now support UInt parameter When there is multiple reference of a io element, the io name win. Add Min/Max functions Update/Fix AXI4 Introduction of MentorDo Fix undeterministic io ordering which could change the generated code (wihtout modifing the beavorial) Compatibility with Verilog 1995 Vhdl compatibility of switch cases for Bits/UInt/SInt with restrictive tool like GHDL