v1.0.5 - *You need to add fork := true into your build.sbt if you want to run tests from sbt command lines* - Now simulation files are emited in the simWorkspace folder by default - You can override the simWorkspace path by setting the SPINALSIM_WORKSPACE environement variable - Clean the why how simulations files are organized - add sim signal.randomize() - Now the VHDL and Verilog backend split long expressions on a multiple assignement. (max 32 expressions per assignement) - Sim waitUntilRisingEdge(count = 100) - SpinalConfig(verbose = true) to print phase timings - Add sim ClockDomain.waitActiveEdgeWhere(cond) - VerilatorBackend now use JNI instread of JNR-FFI to remove a memory leak (it also reduce jar dependancies) - Reduce emited symboles from the Verilator shared object (fix crash when running multiple test from different hardware durring a single VM execution) - SpinalSim is now ready to run multiples tests in multiple threads with multiples hardwares at the same time - Sim API fix toInt (now will return a Int instead than a Long)