v1.1.1 - Fix SpinalSim simulation model (how it manage sensitivity, threads, backend evaluation, commands to write duts signals), this could break some of your testbench (clockdomain.waitUntilXX is now behaving exactly like the equivalent in VHDL/Verilog. In previous version, it was waiting one additional delta cycles) - SpinalSim is now supported in windows - Add SimTimeout - Add Verilator model optimisation flag - Catch Verilator flow exceptions - Better clock crossing error reporting