v1,1,2 - Fix uart decoder boot conditions - Verilator now split files into chunks of 4000 lines to have a faster compilation on big designs - Now the crossclocking check will also walk the clocks paths to see if two clock domains share the same common driver - Add simPublic feature, which allow to read internal signals of the Dut during simulations - MaskedLiteral are can no be compared to each other (usefull for hashmap) - SwitchStatement elements are now able to properly give their code location - Flip a direction less signal now produce a PendingError instead of a SpinalError (Easier to debug) - removing the need for `.` in `.elsewhen`(Thanks soronpo) - SpinalSim run on Mac - Fix assignement overriding detection - SpinalSim add abstract randomize / assignBigInt