v1.1.3 SpinalHDL : - Verilog is now emiting ROM via the verilog memreadb macro - You can keep the verilog inline rom via the inlineRom flag in SpinalConfig - Workaround a VCS 2017 verilog shift issue SpinalSim : - add simulation phase API - add SpinalSim retain/release feature - Add experimental simulation tools for stream - Add SimData