v1.2.0 : HardType update Instead of passing hardware datatype arguements as [T <: Data](dataType : T) and then using cloneOf(dataType), please use [T <: Data](dataType : HardType[T]) and then dataType() It is safer as it remove the usage of the cloneOf and also avoid instanciating a signal into the netlist just for generation purposes. - Add anonymSignalUniqueness feature #144 - Literals are now propagated over one basetype - Fix expression ScalaLocated trigger - Better bit access error reporting - Mem/Vec/Flow/Stream are now using HardType instead of cloneOf(signal) - Hardtype don't instanciate stuff unless it's required - missing unsetRegIfNoAssignementTag now emit a warning instead of a error - Add parameter rtlHeader in SpinalConfig, use to generate a custom header in the rtl file generated - Add bit vectors casting with specific width - Add SpiDdr - Add FlowMonitor - Fix missing attribut postfix on ram - Add a _ postfix in verilog on signals with duplicated names #133 - Fix non deterministic generation - Add SpinalSystemVerilog (emit assertion in a SV way) - Add extra flags option to verilator command - Add `ifndef SYNTHESIS ... `endif around $display - Typo enum encoding Sequancial -> Sequential - fix #134 literal bit width - verilog module's output which are internaly read doesn't generate an intermediat signal anymore - Better Nameable priority control, add RegNext and Delay regs name - fix Qsysify - Fix Apb3Decoder lock on unmapped access - fix mem blackboxing