v1.3.2 - Fix Verilog EnumPoison values - Avoid VHDL enum literal name clash - SpinalSim do an final sleep(1) after simulation crash to save signals state into the netlist - Remove some useless fork from SpinalSim utiles - PipelinedMemoryBusInterconnect allow adding a master without connection - Add some Mem multi port stream read utiles - Improve SimData and the ScoreboardInOrder API - Improve StreamMonitor/FlowMonitor simulation speed - dockerize - Fix wishbone decoder - Fix Wishbone arbiter bug (same as Decoder) - change some setCompositeName usage to weak - Add BusSlaveFactory.read(address, bitId -> xxx, ...) - Vec.read now unfixWidth to allow variable bit widths - Fix Data.clone ast cleaning - Add readLimit into Prescaler.driveFrom - SpinalSim UartDecoder now avoid printing \r - Fix backend when they have to generate a writeFirst Mem.syncRead. (Not it throw an error instead of generating broken VHDL/Verilog - Fix #198 (broken addTags) - Improve signal naming (and avoid Vec index name spreading)