v1.3.8: - add SInt/UInt fixpoint and other usefull method extensions - Fix StateMachine onEntry onExit ordering - JtagTap fix bypass register to allow multiple tap on the chain - BufferCC now get a composite name - add spinal.lib.sim.SparseMemory - Fix PLIC with no interrupts - Apb generators now use Handle for address - Axi4 simulation agent now allow to specify read data - Add Simple BmbToAxi4Bridge - Add AS4C32M16SB timings - SdramXdr allow generation without RESETn feature - Update DDR2 software - Add SdramXdr DDR2 simulations (PASS) - Add MT47H64M16HR layout - Add SdramXdr DDR2 layout - XilinxS7Phy now allow burstlength of 4 - sdram XDR replace BL by ctrlBurstLength - Improve SDRAM timings by generations - sdramModel checkers path fix - Fix tasker multi port active to precharge timings - Add Ecp5Sdrx2Phy - Add ECP5 io blackboxes - fix BmbDecoder - Got SdramXdr inferedSdrPhy to work on hardware - Allow BmbDecoder to manage rsp even if cmd didn't fire - Add ECP5 io blackbox - Add KeepAttribute tooling - Now Both VHDL and Verilog backend emit syncronus reads as don't care readDurrinWrite using separated process for each memory ports. - Add Device.ALTERA, which automaticaly add no_rw_check on don'tcare memories - fix #243 - Fix SpiXdrMasterCtrl full duplex idle MOSI stay now high when idle for better SPI spec compliance - got Xdr Sdram controller to pass SDR model checks - Add Artix 7 STARTUPE2 blackbox - Fix Xdr BmbAdapter refresh handeling - Improve Xdr tester - Fix Xdr backend rsp fifo size - Fix SdramXdr CKE - sdramXdr now use different phases for different commands - Add XdrSdram cocotb model checker - Add Axi arbiter routeBufferM2sPipe - Add lowlatency fifo regressions - SpinalSim allow output clock - Axi arbiters add routeBuffer latency and s2mPipe option - SdramXdr controller stuff fixed, need to improve Tasker timings - Add Smaller and SmallerOrEqual symplifyNode implementation - Add RtlPhy which can be infered by verilator for fast and flexible sim of the XdrSdram controller - Add Stream.repeat - Add sbt-assembly - Add RISC-V machine timer - Add Apb3Monitor/listener - Add Apb3Dummy, usefull to scope APB stuff in simulation - SpinalSim forkStimulus ASYNC now behave as SYNC - add Clock.sync - VerilatorBackend add -Wno-CMPCONST - Fix SpiXdrMasterCtrl without SS - Ram_1wrs now support masked writes - SpiXdrMasterCtrl always give a reset value to ss.activeHigh - Improve StreamFifoCc frequency - Add Axi4CC - Add Axi4Checker - Axi4SharedOnChipRamMultiPort do not support backpresure - Fix artix synthesis bench - add Stream.combStage - Add Axi4Upsizer - Allow HexTools.initRam to work non none 32 bits ram - Fix axi crossbar generation - add AxiReadOnly simulation agents - Axi4 upsized done and tested for INCR burst only - Add spiXdrMasterCtrl pipelining option - Fix Axidecoder when only used with one slave without decodingerror possibility - Merge branch 'blackBoxAsComponent' into dev - allow BB to be emited as regular component - Add Axi4 upsizer, only for INCR bursts - Fix Generator clockdomain - Fix Handle get on lazy default - Now each Generator has its own Handle[ClockDomain] - Add Apb3CC alternative - Fix flow m2sPipe holdPayload