v1.6.1 Mostly fixes and small feature additions - Mem with only 1 entry (translated into register) now allow multiple write ports (allow override) - add OHMasking.roundRobinMaskedFull - add OHMasking.roundRobinMasked - StateFsm now give name to the inner states - add axi4 bus support to Axi4ReadOnlyMonitor. - Add AreaRoot - Add checks to ensure the memory and its ports are correct hearchicaly speaking - Fix BmbToAxi4Bridge - add ScopePropertyContext with mutable and immutable map for better scaling - Add BufferCC.defaultDepth scopeProperty - Add support for write byte enable in BusSlaveFactory.writeMemWordAligned - added BUFGCE (bufg with clock enable) to clocking blackboxes for xilinx - Add lib.logic to infer decoding logic from some Masked specification - MuxOh now check that inputs have the same length - Better Reserved name not free reporting - BitVector.subdivide now have a strict option for non multiple bit lenght - Add AreaObject - Add StreamTransactionExtender. - Add setIdle and setBlocked functions to the axi buses, - spinal.lib now add Seq.groupByLinked - Fix AxiLite4 responses getters - MemWrite fix data width check - Add Module alias to Component in spinal.core - Prevent enum's mux normalizeInputs being applied to the selection exception - Add read/write instructionCtrl to JtagTap that allows for different Input/output data - add Growable.addRet(value) - add Mem.readAsyncPort - unassigned register with init will now emit a error on the first elaboration - add TraversableOnce.distinctLinked - ValCallbackRec can now name LinkedHashSet - add Data.wrapNext - Add Data.freeze() to error on any future assigment - add log2up(Int) - PhaseMemBlackboxing now implement wrapConsumers and removeMem - Add ScopeStatement.on(body) - Fix ClockDomain.apply - Can now apply tags to ClockDomain - Add ClassName object - Add ScopeProperty(defaultValue) construction - Add Mem.fill API - always emit timescale in verilog - fix #520 640x480#60 hz vga timings - deprecated BitVector.range, replaced by bitsRange - add BitVector.valueRange - StreamFifoLowLatency can now use Vec based storage - SpinalSim iverilog can now use includes - SpinalSim now try to figure out if a exception came for the hardware elaboration API - support inline rtl for BlackBox - Move lib.generator.Lock to core.fiber - Add xilinx s7 ff blackbox - Add MuxOH.or - Axi4Crossbar fix addPipelining being applied twice for nodes which are both master and slave at the same time - Remove Axi4Decoder low latency support - Fix Axi4 write decoders when used in low latency mode - Axi4 now handle better the absence of burst signal and id signl - Revert Verilog backend Mem.read multi symbole ram changes (no more xxxx[y : z]) to help inferation - Fix jtagTap bypass (thanks sebastien-riou) - UsbDeviceCtrlTester do not try isochronus on EP0 anymore - Add OhMasking.firstV2 - Component.propagateIo removed (in favor of Data.toIo) - verilog reduction operators now handle zero width signals - Fix empty MultiData comparison - StateMachine whenIsActive now implement priorities. - States implementing the StateCompletionTrait should use whenIsActive with priority 1 to ensure they are called last. - StateMachine.bootAsEntry renamed into makeInstantEntry - Added some size check to Apb3Decoder - Merge branch 'SpinalHDL:dev' into dev - Add Bool ? T otherwise T - add cache for verilator binaries - SpinalSimConfig.compile do not mutate the config anymore - Fix ClockDomainResetGenerator.powerOnReset default value - Add support to give name to Option[Nameable]