v1.6.2 Mostly fixes with a some additions - Verilog backend now implement a better randboot - add OHMasking.roundRobinMaskedInvert - LatencyAnalysis now assert no null arguements - Component postInitCallback now enforce the clockdomain - MemReadPort.bypass added - Regif merged - Fix SpiXdrMasterCtrl definition name being forced - Fix generation of RTS and CTS pins for UartCtrl - SwitchStatement.normalizeInputs fixed for scala 2.13.7+ - SpiXdrMasterCtrl can now be used for more than 8 bits SPI frame and mixed width configurations - Fix non trivial verilog fixed signal are emited by using function (fix sim) - StateMachine build can now be manualy enforced - Fix Scope property push when never set by the past and no default - Fix a few ScopeProperty restore/rework - add more option to axi4 unburstify. - support useSize = false to axi4 unburstify. - Verilator backend no more copy rom bin files to the current directory. - Add downsizer for Axi4 - JtagInstructionWrapper.ignoreWidth added to handle jtag chain (openocd updated too) - Component stub clock/reset removed bug fix - Backends do not check anymore the definition name uniquness of blackboxes (#546) - Add reset function to Axi4 related simulation agents. - Add more Symplify api - Add OhMux - Binary system utils added - Add globalCache(key, factory) - Fix scala 2.13 Apb3Decoder Seq - Fix #553 Verilog /* xx */ for CD BOOT kind - spinal.lib add Repeat(Data, times) - Axi4SlaveFactory now buffer the write responses to avoid some combinatorial link between streams - spinal.lib now implicitly add withBufferedResetFrom function to ClockDomain - add BitVector orMask/andMask