v1.6.4 Mostly 3 fixes : - Nameable.composite now handle the ref owner properly - Fix cross clock pop reset for active low restets - Emited VHDL now check for bit access being out of range In bulk : - Add Bool.asSInt(bitCount) - Vhdl package now check against out of bound - improve component definition name overlap error report - Add SEL handling to WishboneSlaveFactory - Fix asyncAssertSyncDeassertCreateCd reset polarity - add more test configs for the StreamFifoCcTester - #609 add SpinalReport.printZeroWidth() - #608 add Stream.forkSerial - Fix #610 (removePruned=true removing too much) - Add Axilite4 plic/clint - Add support for verilog simple dual port read first - add Any.ifMap(cond)(T => T) - improve the axi4ram design by pipeline stream - use show ahead pattern instead of plain logic. - use queue to break down the bStream and writeStream. - Verilog backend can now emit mux's switch with single target without using begin end - Add mssing code (Nameable.setPartialName with owner) - Add wishbone plic/clint - Add AxiLite4SpecRenamer for read only - Area vallCallbackRec is now able to properly override ref owner