diff --git a/Documentation/devicetree/bindings/perf/hisi-l3t-pmu.txt b/Documentation/devicetree/bindings/perf/hisi-l3t-pmu.txt
new file mode 100644
index 0000000000000000000000000000000000000000..f747d0e8cff361995a0b4fc687978a24e7011902
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/hisi-l3t-pmu.txt
@@ -0,0 +1,17 @@
+Hisilicon L3T PMU comtrollers
+
+Required properties:
+  - compatible : should be "hisilicon,l3t-pmu".
+  - reg : should contain at least address and length of the L3T PMU
+    register set for the device.
+  - interrupts : one L3T interrupt should be described here.
+
+Example
+    l3t0@81170000 {
+        compatible = "hisilicon,l3t-pmu";
+        hisilicon,scl-id = <1>;
+        hisilicon,ccl-id = <0>;
+        hisilicon,index-id = <1>;
+        reg = <0x0 0x81170000 0x0 0x10000>;
+        interrupts = <0x0 316 0x4>;
+    };
diff --git a/Documentation/devicetree/bindings/perf/hisi-lpddrc-pmu.txt b/Documentation/devicetree/bindings/perf/hisi-lpddrc-pmu.txt
new file mode 100644
index 0000000000000000000000000000000000000000..89ebc7e75bc49c3197f565a57f5bb1a02337e99e
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/hisi-lpddrc-pmu.txt
@@ -0,0 +1,16 @@
+Hisilicon LPDDRC PMU comtrollers
+
+Required properties:
+  - compatible : should be "hisilicon,lpddrc-pmu".
+  - reg : should contain at least address and length of the LPDDRC PMU
+    register set for the device.
+  - interrupts : one LPDDRC interrupt should be described here.
+
+Example
+    lpddrc0@A5800000 {
+        compatible = "hisilicon,lpddrc-pmu";
+        hisilicon,ch-id = <0>;
+        hisilicon,scl-id = <1>;
+        reg = <0x0 0xA5800000 0x0 0x10000>;
+        interrupts = <0x0 32 0x4>;
+    };