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  1. Mar 30, 2015
  2. Mar 25, 2015
  3. Mar 19, 2015
    • Mark James's avatar
      ARM: socfpga: dts: fix spi1 interrupt · 1ac31de7
      Mark James authored
      
      The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
      Trying to use the master without this change results in the kernel boot
      process waiting forever for an interrupt that will never occur while
      attempting to probe any slave devices configured in the device tree as being
      under SPI master 1.
      
      The change works for the Cyclone V, and according to the Arria 5 handbook
      should be good there too.
      
      Signed-off-by: default avatarMark James <maj@jamers.net>
      Acked-by: default avatarSteffen Trumtrar <s.trumtrar@pengutronix.de>
      Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
      1ac31de7
    • Tony Lindgren's avatar
      ARM: dts: Fix gpio interrupts for dm816x · 599c376c
      Tony Lindgren authored
      
      Commit 7800064b ("ARM: dts: Add basic dm816x device tree
      configuration") added basic devices for dm816x, but I was not able
      to test the GPIO interrupts earlier until I found some suitable pins
      to test with. We can mux the MMC card detect and write protect pins
      from SD_SDCD and SD_SDWP mode to use a normal GPIO interrupts that
      are also suitable for the MMC subsystem.
      
      This turned out several issues that need to be fixed:
      
      - I set the GPIO type wrong to be compatible with omap3 instead
        of omap4. The GPIO controller on dm816x has EOI interrupt
        register like omap4 and am335x.
      
      - I got the GPIO interrupt numbers wrong as each bank has two
        and we only use one. They need to be set up the same way as
        on am335x.
      
      - The gpio banks are missing interrupt controller related
        properties.
      
      With these changes the GPIO interrupts can be used with the
      MMC card detect pin, so let's wire that up. Let's also mux all
      the MMC lines for completeness while at it.
      
      For the first GPIO bank I tested using GPMC lines temporarily
      muxed to GPIOs on the dip switch 10.
      
      Cc: Brian Hutchinson <b.hutchman@gmail.com>
      Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      599c376c
    • Kishon Vijay Abraham I's avatar
      ARM: dts: dra7: remove ti,hwmod property from pcie phy · 07715533
      Kishon Vijay Abraham I authored
      
      Now that we don't have hwmod entry for pcie PHY remove the
      ti,hwmod property from PCIE PHY's. Otherwise we will get:
      
      platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
      
      Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
      [tony@atomide.com: updated comments]
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      07715533
  4. Mar 18, 2015
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