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Commit 2eac5f28 authored by LeoLiu-oc's avatar LeoLiu-oc Committed by Cheng Jian
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PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports

mainline inclusion
from mainline-5.6.9
commit 299bd044
category: PCI
bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19
CVE: NA

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Adapt to current kernel code

Many Zhaoxin Root Ports and Switch Downstream Ports do provide ACS-like
capability but have no ACS Capability Structure.  Peer-to-Peer transactions
could be blocked between these ports, so add quirk so devices behind them
could be assigned to different IOMMU group.

Link: https://lore.kernel.org/r/20200327091148.5190-4-RaymondPang-oc@zhaoxin.com


Signed-off-by: default avatarRaymond Pang <RaymondPang-oc@zhaoxin.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: default avatarLeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: default avatarHanjun Guo <guohanjun@huawei.com>
Reviewed-by: default avatarLeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: default avatarCheng Jian <cj.chengjian@huawei.com>
parent e82ec73b
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