v0.10.11 -> verilog improvments Time and frequancy DSL now return dedicated class instead of BigInt Verilog backend is Verilator ready Verilog backend support comment attributes on signal Verilog backend now use the = assignement operator in combinatorial always blocks Verilog backend now generate much less intermediate nodes for Bool and Bits stuffs Verilog backend case detection is improved Better error messaging Component PrePopTask is now recusivly flushed