Tags

v1.7.0

Two new main features :

1) Formal verification is now in a good state
- SymbiYosys integration, ex FormalConfig.withBMC(15).doVerify(..)
- Added anyconst/anyseq/... support
- Documented in https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html

2) AFix floating point added (experimental, subject to changes)
- Unifie unsigned/signed handeling
- Tracking the exact range of possible values

v1.6.4

Mostly 3 fixes :
- Nameable.composite now handle the ref owner properly
- Fix cross clock pop reset for active low restets
- Emited VHDL now check for bit access being out of range

In bulk :
- Add Bool.asSInt(bitCount)
- Vhdl package now check against out of bound
- improve component definition name overlap error report
- Add SEL handling to WishboneSlaveFactory
- Fix asyncAssertSyncDeassertCreateCd reset polarity
- add more test configs for the StreamFifoCcTester
- #609 add SpinalReport.printZeroWidth()
- #608 add Stream.forkSerial
- Fix #610 (removePruned=true removing too much)
- Add Axilite4 plic/clint
- Add support for verilog simple dual port read first
- add Any.ifMap(cond)(T => T)
- improve the axi4ram design by pipeline stream
- use show ahead pattern instead of plain logic.
- use queue to break down the bStream and writeStream.
- Verilog backend can now emit mux's switch with single target without using begin end
- Add mssing code (Nameable.setPartialName with owner)
- Add wishbone plic/clint
- Add AxiLite4SpecRenamer for read only
- Area vallCallbackRec is now able to properly override ref owner

v1.6.2

Mostly fixes with a some additions

- Verilog backend now implement a better randboot
- add OHMasking.roundRobinMaskedInvert
- LatencyAnalysis now assert no null arguements
- Component postInitCallback now enforce the clockdomain
- MemReadPort.bypass added
- Regif merged
- Fix SpiXdrMasterCtrl definition name being forced
- Fix generation of RTS and CTS pins for UartCtrl
- SwitchStatement.normalizeInputs fixed for scala 2.13.7+
- SpiXdrMasterCtrl can now be used for more than 8 bits SPI frame and mixed width configurations
- Fix non trivial verilog fixed signal are emited by using function (fix sim)
- StateMachine build can now be manualy enforced
- Fix Scope property push when never set by the past and no default
- Fix a few ScopeProperty restore/rework
- add more option to axi4 unburstify.
- support useSize = false to axi4 unburstify.
- Verilator backend no more copy rom bin files to the current directory.
- Add downsizer for Axi4
- JtagInstructionWrapper.ignoreWidth added to handle jtag chain (openocd updated too)
- Component stub clock/reset removed bug fix
- Backends do not check anymore the definition name uniquness of blackboxes (#546)
- Add reset function to Axi4 related simulation agents.
- Add more Symplify api
- Add OhMux
- Binary system utils added
- Add globalCache(key, factory)
- Fix scala 2.13 Apb3Decoder Seq
- Fix #553 Verilog /* xx */ for CD BOOT kind
- spinal.lib add Repeat(Data, times)
- Axi4SlaveFactory now buffer the write responses to avoid some combinatorial link between streams
- spinal.lib now implicitly add withBufferedResetFrom function to ClockDomain
- add BitVector orMask/andMask

v1.6.1

Mostly fixes and small feature additions

- Mem with only 1 entry (translated into register) now allow multiple write ports (allow override)
- add OHMasking.roundRobinMaskedFull
- add OHMasking.roundRobinMasked
- StateFsm now give name to the inner states
- add axi4 bus support to Axi4ReadOnlyMonitor.
- Add AreaRoot
- Add checks to ensure the memory and its ports are correct hearchicaly speaking
- Fix BmbToAxi4Bridge
- add ScopePropertyContext with mutable and immutable map for better scaling
- Add BufferCC.defaultDepth scopeProperty
- Add support for write byte enable in BusSlaveFactory.writeMemWordAligned
- added BUFGCE (bufg with clock enable) to clocking blackboxes for xilinx
- Add lib.logic to infer decoding logic from some Masked specification
- MuxOh now check that inputs have the same length
- Better Reserved name not free reporting
- BitVector.subdivide now have a strict option for non multiple bit lenght
- Add AreaObject
- Add StreamTransactionExtender.
- Add setIdle and setBlocked functions to the axi buses,
- spinal.lib now add Seq.groupByLinked
- Fix AxiLite4 responses getters
- MemWrite fix data width check
- Add Module alias to Component in spinal.core
- Prevent enum's mux normalizeInputs being applied to the selection exception
- Add read/write instructionCtrl to JtagTap that allows for different Input/output data
- add Growable.addRet(value)
- add Mem.readAsyncPort
- unassigned register with init will now emit a error on the first elaboration
- add TraversableOnce.distinctLinked
- ValCallbackRec can now name LinkedHashSet
- add Data.wrapNext
- Add Data.freeze()  to error on any future assigment
- add log2up(Int)
- PhaseMemBlackboxing now implement wrapConsumers and removeMem
- Add ScopeStatement.on(body)
- Fix ClockDomain.apply
- Can now apply tags to ClockDomain
- Add ClassName object
- Add ScopeProperty(defaultValue) construction
- Add Mem.fill API
- always emit timescale in verilog
- fix #520 640x480#60 hz vga timings
- deprecated BitVector.range, replaced by bitsRange
- add BitVector.valueRange
- StreamFifoLowLatency can now use Vec based storage
- SpinalSim iverilog can now use includes
- SpinalSim now try to figure out if a exception came for the hardware elaboration API
- support inline rtl for BlackBox
- Move lib.generator.Lock to core.fiber
- Add xilinx s7 ff blackbox
- Add MuxOH.or
- Axi4Crossbar fix addPipelining being applied twice for nodes which are both master and slave at the same time
- Remove Axi4Decoder low latency support
- Fix Axi4 write decoders when used in low latency mode
- Axi4 now handle better the absence of burst signal and id signl
- Revert Verilog backend Mem.read multi symbole ram changes (no more xxxx[y : z]) to help inferation
- Fix jtagTap bypass (thanks sebastien-riou)
- UsbDeviceCtrlTester do not try isochronus on EP0 anymore
- Add OhMasking.firstV2
- Component.propagateIo removed (in favor of Data.toIo)
- verilog reduction operators now handle zero width signals
- Fix empty MultiData comparison
- StateMachine whenIsActive now implement priorities.
- States implementing the StateCompletionTrait should use whenIsActive with priority 1 to ensure they are called last.
- StateMachine.bootAsEntry renamed into makeInstantEntry
- Added some size check to Apb3Decoder
- Merge branch 'SpinalHDL:dev' into dev
- Add Bool ? T otherwise T
- add cache for verilator binaries
- SpinalSimConfig.compile do not mutate the config anymore
- Fix ClockDomainResetGenerator.powerOnReset default value
- Add support to give name to Option[Nameable]

v1.6.0

This version has 3 main things :

1) It fix some clockdomain crossing issues in the StreamCcByToggle and FlowCcByToggle.
2) It add Scala 2.13 support
3) Because of the scala 2.13 support and the preparation for scala 3 support, it has to drop some syntax. Now if you want do define a Bool signal, you need to write Bool() / in Bool() / out Bool()

It also fix the Axi.incr issues with verilator, the ethernet cross clock domain and a few other things.

v1.5.0

This update bring many fixes and improvement, notably :

1) Better naming

There will now be much less unamed signals in the generated netlists.
In addition, the Composite class feature was added to define relative namespace in a smooth way.

See https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Structuring/naming.html# for more information and examples.

2) Fiber API

This allow to generate hardware using a similar paradigm than the Scala Future.

See https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Libraries/fiber.html for more info.

3) A USB OHCI controller (usb host low/full speed)

v1.4.2

Many addition, many fixes. but mostly GHDL/iverilog are now supported in SpinalSim

v1.4.0

Important, this new version now use a scala compiler plugin to improve internals of the language. Consequently, you need to enable that plugin in your project, to do so in SBT, see :
https://github.com/SpinalHDL/SpinalTemplateSbt/commit/b524ddddd830d7e9e7d76604b0d593bb897c7229#diff-fdc3abdfd754eeb24090dbd90aeec2ce

Another API change is the removal of implicit String to B/U/S convertion, so you can't do anymore (myUInt + "0001"), instead you have to do (myUInt + U"0001").

Other changes are :
- SpinalSim now support directories with spaces
- Verilator compilation is now multithreaded
- Fix SpinalSim seed
- lib.Bench now use a environnement variable by default
- Remove deprecated doManagedSim
- Improve doSim API
- added ECP5 JTAGG Blackbox
- synthesis targets now use environnement variable to find tools path
- Fix I2cCtrl SDA/SCL driving
- Fix SpinalSim.addRtl on windows
- Add Component.afterElaboration as a clean replacement of addPrePopTask
- Better verilog formating
- Bits method extention
- Stream add clearValidWhen
- AhbLite3 incr beatCounter only when HTRANS == SEQ or NONSEQ
- Add a few null assert in the expression to have null issues detected at user elaboration time
- Add Anlogic Eagle BRAM to BMB
- improve generator naming using idsl
- Add Long to Bits/UInt/SInt implicits
- SpinalSim add a pre sim dut eval to propagate constants
- BlackBox mapClockDomain now support reset/enable polarity adaptation
- Fix enumeration undeterministic generation order
- Now the default assert severity is FAILURE
- SpinalSim now handle Verilator assertion failure
- UartCtrl now allow more than 255 fifo depth, support break, support CTS RTS
- fix readStreamNonBlocking for multi-word case
- Add StreamMux, StreamCombinerSequential, StreamForkSimple
- Stream::transmuteWith
- Add StreamForkSimple
- Emit proper assert/assume/cover statements in Verilog

v1.3.8:

- add SInt/UInt fixpoint and other usefull method extensions
- Fix StateMachine onEntry onExit ordering
- JtagTap fix bypass register to allow multiple tap on the chain
- BufferCC now get a composite name
- add spinal.lib.sim.SparseMemory
- Fix PLIC with no interrupts
- Apb generators now use Handle for address
- Axi4 simulation agent now allow to specify read data
- Add Simple BmbToAxi4Bridge
- Add AS4C32M16SB timings
- SdramXdr allow generation without RESETn feature
- Update DDR2 software
- Add SdramXdr DDR2 simulations (PASS)
- Add MT47H64M16HR layout
- Add SdramXdr DDR2 layout
- XilinxS7Phy now allow burstlength of 4
- sdram XDR replace BL by ctrlBurstLength
- Improve SDRAM timings by generations
- sdramModel checkers path fix
- Fix tasker multi port active to precharge timings
- Add Ecp5Sdrx2Phy
- Add ECP5 io blackboxes
- fix BmbDecoder
- Got SdramXdr inferedSdrPhy to work on hardware
- Allow BmbDecoder to manage rsp even if cmd didn't fire
- Add ECP5 io blackbox
- Add KeepAttribute tooling
- Now Both VHDL and Verilog backend emit syncronus reads as don't care readDurrinWrite using separated process for each memory ports.
- Add Device.ALTERA, which automaticaly add no_rw_check on don'tcare memories
- fix #243
- Fix SpiXdrMasterCtrl full duplex idle MOSI stay now high when idle for better SPI spec compliance
- got Xdr Sdram controller to pass SDR model checks
- Add Artix 7 STARTUPE2 blackbox
- Fix Xdr BmbAdapter refresh handeling
- Improve Xdr tester
- Fix Xdr backend rsp fifo size
- Fix SdramXdr CKE
- sdramXdr now use different phases for different commands
- Add XdrSdram cocotb model checker
- Add Axi arbiter routeBufferM2sPipe
- Add lowlatency fifo regressions
- SpinalSim allow output clock
- Axi arbiters add routeBuffer latency and s2mPipe option
- SdramXdr controller stuff fixed, need to improve Tasker timings
- Add Smaller and SmallerOrEqual symplifyNode implementation
- Add RtlPhy which can be infered by verilator for fast and flexible sim of the XdrSdram controller
- Add Stream.repeat
- Add sbt-assembly
- Add RISC-V machine timer
- Add Apb3Monitor/listener
- Add Apb3Dummy, usefull to scope APB stuff in simulation
- SpinalSim forkStimulus ASYNC now behave as SYNC
- add Clock.sync
- VerilatorBackend add -Wno-CMPCONST
- Fix SpiXdrMasterCtrl without SS
- Ram_1wrs now support masked writes
- SpiXdrMasterCtrl always give a reset value to ss.activeHigh
- Improve StreamFifoCc frequency
- Add Axi4CC
- Add Axi4Checker
- Axi4SharedOnChipRamMultiPort do not support backpresure
- Fix artix synthesis bench
- add Stream.combStage
- Add Axi4Upsizer
- Allow HexTools.initRam to work non none 32 bits ram
- Fix axi crossbar generation
- add AxiReadOnly simulation agents
- Axi4 upsized done and tested for INCR burst only
- Add spiXdrMasterCtrl pipelining option
- Fix Axidecoder when only used with one slave without decodingerror possibility
- Merge branch 'blackBoxAsComponent' into dev
- allow BB to be emited as regular component
- Add Axi4 upsizer, only for INCR bursts
- Fix Generator clockdomain
- Fix Handle get on lazy default
- Now each Generator has its own Handle[ClockDomain]
- Add Apb3CC alternative
- Fix flow m2sPipe holdPayload

v1.3.6

minor fixes and Generator + Bmb improvments

v1.3.5

Improve simulation agent speed
Add Generator abstraction
Add BMB bus, decoder, arbiter, interconnect
More fragment utilities

v1.3.4

Fix #206, Add width assertion on Bool.assignFromBits
Fix component substitution due to Component case classes equality checks
Fix Data.pull name propagation
Ahb mask generation : fix Verilator lint complaints
Ahb crossbar allow address downsizing
Add Axi4 low latency option
Fix some Axi4 crossbar config issues
Add Apb3InterruptCtrl

v1.3.3
Fix BusSlaveFactory double underscore name generation
Blackbox - Add default value of the generic in the definition of the entity in VHDL
Add B(Seq[Bool]) cast
Fix Nameable reflect name for componentless stuff
Fix switch statements no triggering the scala location collection

v1.3.2

- Fix Verilog EnumPoison values
- Avoid VHDL enum literal name clash
- SpinalSim do an final sleep(1) after simulation crash to save signals state into the netlist
- Remove some useless fork from SpinalSim utiles
- PipelinedMemoryBusInterconnect allow adding a master without connection
- Add some Mem multi port stream read utiles
- Improve SimData and the ScoreboardInOrder API
- Improve StreamMonitor/FlowMonitor simulation speed
- dockerize
- Fix wishbone decoder
- Fix Wishbone arbiter bug (same as Decoder)
- change some setCompositeName usage to weak
- Add BusSlaveFactory.read(address, bitId -> xxx, ...)
- Vec.read now unfixWidth to allow variable bit widths
- Fix Data.clone ast cleaning
- Add readLimit into Prescaler.driveFrom
- SpinalSim UartDecoder now avoid printing \r
- Fix backend when they have to generate a writeFirst Mem.syncRead. (Not it throw an error instead of generating broken VHDL/Verilog
- Fix #198 (broken addTags)
- Improve signal naming (and avoid Vec index name spreading)

v1.3.1

- Add SpinalConfig.randBootFixValue  to randomize or not the signals set with randBoot()
- Bundle created from HardTypes now keep a reference to him for future clones
- Fix library eviction messages #171
- For each enum signal in the generated verilog there is now a string signal to get a waveform friendly state value.
- Simulation ClockDomain.forkStimulus return Unit now
- Improve SpinalSim performance by remove debugging asserts
- workaround cadence incisive 15.20 VHDL bug (not expression)
- Add Data.as(anotherType) casting
- Fix AXI4 incr address for unaligned accesses
- Add SpinalConfig.withPrivateNamespace feature (toplevel's children components get the toplevel definition name as prefix)
- deprecate kB, MB, ..   to KiB, MiB
- Fix AvalonMMSlaveFactory