Documentation: Add documentation for Hisilicon SoC PMU DTS binding

ascend inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4D4WR


CVE: NA

---------------------------

Driver providing perf backend for LPDDRC and L3T PMU hardware
found in Hisilicon Soc.

Signed-off-by: Fang Lijun <fanglijun3@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>

Documentation/devicetree/bindings/perf/hisi-l3t-pmu.txt

+Hisilicon L3T PMU comtrollers
+
+Required properties:
+  - compatible : should be "hisilicon,l3t-pmu".
+  - reg : should contain at least address and length of the L3T PMU
+    register set for the device.
+  - interrupts : one L3T interrupt should be described here.
+
+Example
+    l3t0@81170000 {
+        compatible = "hisilicon,l3t-pmu";
+        hisilicon,scl-id = <1>;
+        hisilicon,ccl-id = <0>;
+        hisilicon,index-id = <1>;
+        reg = <0x0 0x81170000 0x0 0x10000>;
+        interrupts = <0x0 316 0x4>;
+    };

Documentation/devicetree/bindings/perf/hisi-lpddrc-pmu.txt

+Hisilicon LPDDRC PMU comtrollers
+
+Required properties:
+  - compatible : should be "hisilicon,lpddrc-pmu".
+  - reg : should contain at least address and length of the LPDDRC PMU
+    register set for the device.
+  - interrupts : one LPDDRC interrupt should be described here.
+
+Example
+    lpddrc0@A5800000 {
+        compatible = "hisilicon,lpddrc-pmu";
+        hisilicon,ch-id = <0>;
+        hisilicon,scl-id = <1>;
+        reg = <0x0 0xA5800000 0x0 0x10000>;
+        interrupts = <0x0 32 0x4>;
+    };