- Apr 07, 2021
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LeoLiu-oc authoredmainline inclusion from mainline-5.5 commit b971880f category: x86/Kconfig bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- AMD 2nd generation EPYC processors support the UMIP (User-Mode Instruction Prevention) feature. So, rename X86_INTEL_UMIP to generic X86_UMIP and modify the text to cover both Intel and AMD. [ bp: take of the disabled-features.h copy in tools/ too. ] Signed-off-by:
Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "x86@kernel.org" <x86@kernel.org>
Link: https://lkml.kernel.org/r/157298912544.17462.2018334793891409521.stgit@naples-babu.amd.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Some ACPI devices need to issue dma requests to access the reserved memory area.BIOS uses the device scope type ACPI_NAMESPACE_DEVICE in RMRR to report these ACPI devices. This patch add support for detecting ACPI devices in RMRR and in order to distinguish it from PCI device, some interface functions are modified. This patch was submitted to mainline kernel but not accepted by upstream maintainer whose reason is "As I explained in the previous reply, RMRRs were added as work around for certain legacy device and we have been working hard to fix those legacy devices so that RMRR are no longer needed. Any new use case of RMRR is not encouraged". VT-D 1.3/2.5/3.0 Spec have this case's specification, We think this Intel driver should support this case too. References: https://lkml.org/lkml/2020/10/10/56 Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- This bug is found in Zhaoxin platform, but it's a commom code bug. Fail sequence: step1: Unbind UHCI controller from native driver; step2: Bind UHCI controller to vfio-pci, which will put UHCI controller in one vfio group's device list and set UHCI's dev->driver_data to struct vfio-pci(for UHCI) step3: Unbind EHCI controller from native driver, will try to tell UHCI native driver that "I'm removed by set companion_hcd->self.hs_companion to NULL. However, companion_hcd get from UHCI's dev->driver_data that has modified by vfio-pci already.So, the vfio-pci structure will be damaged! step4: Bind EHCI controller to vfio-pci driver, which will put EHCI controller in the same vfio group as UHCI controller; ... ... step5: Unbind UHCI controller fr...
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LeoLiu-oc authored
mainline inclusion from mainline-5.6 commit 0f378d73 category: x86/apic bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- When a system suspends, the local APIC is disabled in the suspend sequence, but the IOAPIC is left in the current state. This means unmasked interrupt lines stay unmasked. This is usually the case for IOAPIC pin 9 to which the ACPI interrupt is connected. That means that in suspended state the IOAPIC can respond to an external interrupt, e.g. the wakeup via keyboard/RTC/ACPI, but the interrupt message cannot be handled by the disabled local APIC. As a consequence the Remote IRR bit is set, but the local APIC does not send an EOI to acknowledge it. This causes the affected interrupt line to become stale and the stale Remote IRR bit will cause a hang when __synchronize_hardirq() is invoked for that interrupt line. To prevent this, mask all IOAPIC entries before disabling the local APIC. The resume code already has the unmask operation inside. [ tglx: Massaged changelog ] Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/1579076539-7267-1-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- On Zhaoxin ZX-100 project, xHCI can't work normally after resume from system Sx state. To fix this issue, when resume from system sx state, reinitialize xHCI instead of restore. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Over Current condition is not standardized in the UHCI spec. Zhaoxin UHCI controllers report Over Current active off. Intel controllers report it active on, so we'll adjust the bit value. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add Zhaoxin NB HDAC codec support. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add the new PCI ID 0x1d17 0x9141/0x9142/0x9144 Zhaoxin NB HDAC support. And add some special initialization for Zhaoxin NB HDAC. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Conflicts:
azx_interrupt in sound/pci/hda/hda_controller.c
[Cheng Jian: adjust context]
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add the new PCI ID 0x1d17 0x3288 Zhaoxin SB HDAC support. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Some Zhaoxin xHCI controllers follow usb3.1 spec, but only support gen1 speed 5G. While in Linux kernel, if xHCI suspport usb3.1,root hub speed will show on 10G. To fix this issue, read usb speed ID supported by xHCI to determine root hub speed. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- On some Zhaoxin platforms, xHCI will prefetch TRB for performance improvement. However this TRB prefetch mechanism may cross page boundary, which may access memory not belong to xHCI. In order to fix this issue, using two pages for TRB allocate and only the first page will be used. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Conflicts:
drivers/usb/host/xhci.h for XHCI_ZHAOXIN_TRB_FETCH
drivers/usb/host/xhci.c for xhci_pci_quirks
[Cheng Jian: adjust context]
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.6.9 commit 299bd044 category: PCI bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Adapt to current kernel code Many Zhaoxin Root Ports and Switch Downstream Ports do provide ACS-like capability but have no ACS Capability Structure. Peer-to-Peer transactions could be blocked between these ports, so add quirk so devices behind them could be assigned to different IOMMU group. Link: https://lore.kernel.org/r/20200327091148.5190-4-RaymondPang-oc@zhaoxin.com Signed-off-by:
Raymond Pang <RaymondPang-oc@zhaoxin.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.6.9 commit 0325837c category: PCI bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Some Zhaoxin endpoints are implemented as multi-function devices without an ACS capability, but they actually don't support peer-to-peer transactions. Add ACS quirks to declare DMA isolation. Link: https://lore.kernel.org/r/20200327091148.5190-3-RaymondPang-oc@zhaoxin.com Signed-off-by:
Raymond Pang <RaymondPang-oc@zhaoxin.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Conflicts:
drivers/pci/quirks.c
[Cheng Jian: adjust context]
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add LPM u1/u2 feature support for xHCI of zhaoxin The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Conflicts:
drivers/usb/host/xhci.h
drivers/usb/host/xhci.c
[Cheng Jian: adjust context]
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add Zhaoxin Serial ATA support for Zhaoxin CPUs. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.6.9 commit 33755906 category: PCI bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add Zhaoxin Vendor ID to pci_ids.h Link: https://lore.kernel.org/r/20200327091148.5190-2-RaymondPang-oc@zhaoxin.com Signed-off-by:
Raymond Pang <RaymondPang-oc@zhaoxin.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.8 commit 3a4ac121 category: x86/perf bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add the generic Zhaoxin uncore PMU support. Zhaoxin CPU has provided facilities for monitoring performance via PMU (Performance Monitor Unit), but the functionality is unused so far. Therefore, add support for zhaoxin pmu to make performance related hardware events available. The PMU is mostly an Intel Architectural PerfMon-v2 with a novel errata for the ZXC line. It supports the following events: ----------------------------------------------------------------------------------------------------------------------------------- Event | Event | Umask | Description | Select | | ----------------------------------------------------------------------------------------------------------------------------------- cpu-cycles | 82h | 00h | unhalt core clock instructions | 00h | 00h | number of instructions at retirement. cache-references | 15h | 05h | number of fillq pushs at the current cycle. cache-misses | 1ah | 05h | number of l2 miss pushed by fillq. branch-instructions | 28h | 00h | counts the number of branch instructions retired. branch-misses | 29h | 00h | mispredicted branch instructions at retirement. bus-cycles | 83h | 00h | unhalt bus clock stalled-cycles-frontend | 01h | 01h | Increments each cycle the # of Uops issued by the RAT to RS. stalled-cycles-backend | 0fh | 04h | RS0/1/2/3/45 empty L1-dcache-loads | 68h | 05h | number of retire/commit load. L1-dcache-load-misses | 4bh | 05h | retired load uops whose data source followed an L1 miss. L1-dcache-stores | 69h | 06h | number of retire/commit Store,no LEA L1-dcache-store-misses | 62h | 05h | cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement. L1-icache-loads | 00h | 03h | number of l1i cache access for valid normal fetch,including un-cacheable access. L1-icache-load-misses | 01h | 03h | number of l1i cache miss for valid normal fetch,including un-cacheable miss. L1-icache-prefetches | 0ah | 03h | number of prefetch. L1-icache-prefetch-misses | 0bh | 03h | number of prefetch miss. dTLB-loads | 68h | 05h | number of retire/commit load dTLB-load-misses | 2ch | 05h | number of load operations miss all level tlbs and cause a tablewalk. dTLB-stores | 69h | 06h | number of retire/commit Store,no LEA dTLB-store-misses | 30h | 05h | number of store operations miss all level tlbs and cause a tablewalk. dTLB-prefetches | 64h | 05h | number of hardware pte prefetch requests dispatched out of the prefetch FIFO. dTLB-prefetch-misses | 65h | 05h | number of hardware pte prefetch requests miss the l1d data cache. iTLB-load | 00h | 00h | actually counter instructions. iTLB-load-misses | 34h | 05h | number of code operations miss all level tlbs and cause a tablewalk. ----------------------------------------------------------------------------------------------------------------------------------- Reported-by:
kbuild test robot <lkp@intel.com>
Signed-off-by: CodyYao-oc <CodyYao-oc@zhaoxin.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1586747669-4827-1-git-send-email-CodyYao-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. On platforms with Zhaoxin CPUs supporting this X86 feature, when crc32c-intel and crc32c-generic are both registered, system will use crc32c-intel because its .cra_priority is greater than crc32c-generic. When doing lmbench3 Create and Delete file test on partitions with ext4 enabling metadata checksum, found using crc32c-generic driver could get about 20% performance gain than using the driver crc32c-intel on some Zhaoxin CPUs. This case expect to use crc32c-generic driver for these Zhaoxin CPUs to get performance gain, so remove these Zhaoxin CPUs support from crc32c-intel. This patch was submitted to mainline kernel but not accepted by upstream maintainer whose reason is "Then create a BUG flag for it,". We think this is not a CPU bug for Zhaoxin CPUs. So should patch the crc32c driver for Zhaoxin CPUs but not report a BUG. References: https://lkml.org/lkml/2020/12/11/308 Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.6 commit a84de2fa category: x86/speculation/swapgs bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- New Zhaoxin family 7 CPUs are not affected by the SWAPGS vulnerability. So mark these CPUs in the cpu vulnerability whitelist accordingly. Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/1579227872-26972-3-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.6 commit 1e41a766 category: x86/speculation/spectre_v2 bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- New Zhaoxin family 7 CPUs are not affected by SPECTRE_V2. So define a separate cpu_vuln_whitelist bit NO_SPECTRE_V2 and add these CPUs to the cpu vulnerability whitelist. Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/1579227872-26972-2-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.5 commit 70f0c230 category: x86/mce bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add support for more Zhaoxin CPUs. Newer Zhaoxin CPUs support LMCE compatible with Intel. Add support for that. [ bp: Export functions and massage. ] Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: CooperYan@zhaoxin.com
Cc: DavidWang@zhaoxin.com
Cc: HerryYang@zhaoxin.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: QiyuanWang@zhaoxin.com
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1568787573-1297-5-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.5 commit 5a3d56a0 category: x86/mce bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add support for more Zhaoxin CPUs. All newer Zhaoxin CPUs support CMCI and are compatible with Intel's Machine-Check Architecture. Add that support for Zhaoxin CPUs. [ bp: Massage comments and export intel_init_cmci(). ] Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: CooperYan@zhaoxin.com
Cc: DavidWang@zhaoxin.com
Cc: HerryYang@zhaoxin.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: QiyuanWang@zhaoxin.com
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1568787573-1297-4-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.5 commit 6e898d2b category: x86/mce bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add support for more Zhaoxin CPUs. All newer Zhaoxin CPUs are compatible with Intel's Machine-Check Architecture, so add support for them. [ bp: Reflow comment in vendor_disable_error_reporting() and massage commit message. ] Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: CooperYan@zhaoxin.com
Cc: DavidWang@zhaoxin.com
Cc: HerryYang@zhaoxin.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: QiyuanWang@zhaoxin.com
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1568787573-1297-2-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.2 commit f8c0e061 category: x86/acpi/cstate bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all recent Zhaoxin platforms ARB_DISABLE is a nop. So set related flags correctly in the same way as Intel does. Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5e98@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.2 commit 987ddbe4 category: x86/power bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- For new Centaur CPUs the ucode will take care of the preservation of cache coherence between CPU cores in C-states regardless of how deep the C-states are. So, it is not necessary to flush the caches in software befor entering C3. This useless operation will cause performance drop for the cores which share some caches with the idling core. Signed-off-by:
David Wang <davidwang@zhaoxin.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: brucechang@via-alliance.com
Cc: cooperyan@zhaoxin.com
Cc: len.brown@intel.com
Cc: linux-pm@kernel.org
Cc: qiyuanwang@zhaoxin.com
Cc: rjw@rjwysocki.net
Cc: timguo@zhaoxin.com
Link: http://lkml.kernel.org/r/1545900110-2757-1-git-send-email-davidwang@zhaoxin.com
[ Tidy up the comment. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.3 commit 773b2f30 category: ACPI bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI driver support for it. Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/d1cfd937dabc44518d42038b55522c53@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Detect the extended topology information of Zhaoxin CPUs if available. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
zhaoxin inclusion category: feature bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add Zhaoxin feature bits on Zhaoxin CPUs. The patch is scheduled to be submitted to the kernel mainline in 2021. Signed-off-by:
LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.9 commit 33b4711d category: x86/cpu bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add Centaur family >=7 CPUs specific initialization support. Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link:https://lkml.kernel.org/r/1599562666-31351-3-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.9 commit 8687bdc0 category: x86/cpu bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Use a normal if statements instead of a two-condition switch-case. [ bp: Massage commit message. ] Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/1599562666-31351-2-git-send-email-TonyWWang-oc@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.6 commit 283bab98 category: x86/cpu bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Both functions call init_intel_cacheinfo() which computes L2 and L3 cache sizes from CPUID(4). But then they also call cpu_detect_cache_sizes() a bit later which computes ->x86_tlbsize and L2 size from CPUID(80000006). However, the latter call is not needed because - on these CPUs, CPUID(80000006).EBX for ->x86_tlbsize is reserved - CPUID(80000006).ECX for the L2 size has the same result as CPUID(4) Therefore, remove the latter call to simplify the code. [ bp: Rewrite commit message. ] Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/1579075257-6985-1-git-send-email-TonyWWang-oc@zhaoxin
.
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
LeoLiu-oc authored
mainline inclusion from mainline-5.2 commit 761fdd5e category: x86/cpu bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ---------------------------------------------------------------- Add x86 architecture support for new Zhaoxin processors. Carve out initialization code needed by Zhaoxin processors into a separate compilation unit. To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN for system recognition. Signed-off-by:
Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/01042674b2f741b2aed1f797359bdffb@zhaoxin.com
Signed-off-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
Mathias Nyman authored
mainline inclusion from mainline-5.6.rc3 commit a3ae87dc category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ----------------------------------------------------------- commit a3ae87dc upstream. Intel Comet Lake based platform require the XHCI_PME_STUCK_QUIRK quirk as well. Without this xHC can not enter D3 in runtime suspend. Cc: stable@vger.kernel.org Signed-off-by:
Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20200210134553.9144-5-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
Mathias Nyman authored
mainline inclusion from mainline-5.6.rc3 commit cf0ee7c6 category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ----------------------------------------------------------- commit cf0ee7c6 upstream. xhci driver assumed that xHC controllers have at most one custom supported speed table (PSI) for all usb 3.x ports. Memory was allocated for one PSI table under the xhci hub structure. Turns out this is not the case, some controllers have a separate "supported protocol capability" entry with a PSI table for each port. This means each usb3 roothub port can in theory support different custom speeds. To solve this, cache all supported protocol capabilities with their PSI tables in an array, and add pointers to the xhci port structure so that every port points to its capability entry in the array. When creating the SuperSpeedPlus USB Device Capability BOS descriptor for the xhci USB 3.1 roothub we for now will use only data from the first USB 3.1 capable protocol capability entry in the array. This could be improved later, this patch focuses resolving the memory leak. Reported-by:
Paul Menzel <pmenzel@molgen.mpg.de>
Reported-by: Sajja Venkateswara Rao <VenkateswaraRao.Sajja@amd.com>
Fixes: 47189098 ("xhci: parse xhci protocol speed ID list for usb 3.1 usage")
Cc: stable <stable@vger.kernel.org> # v4.4+
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20200211150158.14475-1-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
Mathias Nyman authored
mainline inclusion from mainline-5.6.9 commit 024d411e category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ----------------------------------------------------------- commit 024d411e upstream. Intel hosts that need the XHCI_PME_STUCK_QUIRK flag should enable runtime pm by calling xhci_pme_acpi_rtd3_enable() before usb_hcd_pci_probe() calls pci_dev_run_wake(). Otherwise usage count for the device won't be decreased, and runtime suspend is prevented. usb_hcd_pci_probe() only decreases the usage count if device can generate run-time wake-up events, i.e. when pci_dev_run_wake() returns true. This issue was exposed by pci_dev_run_wake() change in commit 8feaec33 ("PCI / PM: Always check PME wakeup capability for runtime wakeup support") and should be backported to kernels with that change Cc: <stable@vger.kernel.org> # 4.13+ Signed-off-by:
Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20200210134553.9144-4-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
Mathias Nyman authored
mainline inclusion from mainline-5.6-rc3 commit f148b9f4 category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA ----------------------------------------------------------- commit f148b9f4 upstream. A Full-speed bulk USB audio device (DJ-Tech CTRL) with a invalid Maximum Packet Size of 4 causes a xHC "Parameter Error" at enumeration. This is because valid Maximum packet sizes for Full-speed bulk endpoints are 8, 16, 32 and 64 bytes. Hosts are not required to support other values than these. See usb 2 specs section 5.8.3 for details. The device starts working after forcing the maximum packet size to 8. This is most likely the case with other devices as well, so force the maximum packet size to a valid range. Cc: stable@vger.kernel.org Reported-by:
Rene D Obermueller <cmdrrdo@gmail.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20200210134553.9144-2-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com>
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- Apr 01, 2021
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Yang Yingliang authored
driver inclusion category: feature bugzilla: 34535 CVE: NA Make CONFIG_BMA=m, except euleros_defconfig. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
Naixin Yu authored
driver inclusion category: feature bugzilla: 34535 CVE: NA The BMA software is a system management software offered by Huawei. It supports the status monitoring, performance monitoring, and event monitoring of various components, including server CPUs, memory, hard disks, NICs, IB cards, PCIe cards, RAID controller cards, and optical modules. The host_kbox_drv driver serves the function of a black box. When a panic or mce event happen to the system, it will record the event time, system's status and system logs and send them to BMC before the OS shutdown. This driver depends on the host_edms_drv driver. Link: https://lkml.org/lkml/2020/6/22/752 Signed-off-by:
Naixin Yu <yunaixin@huawei.com>
Reviewed-by: Wang Qindong <wangqindong@huawei.com>
Acked-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
Naixin Yu authored
driver inclusion category: feature bugzilla: 34535 CVE: NA The BMA software is a system management software offered by Huawei. It supports the status monitoring, performance monitoring, and event monitoring of various components, including server CPUs, memory, hard disks, NICs, IB cards, PCIe cards, RAID controller cards, and optical modules. This cdev_veth_drv driver is one of the communication drivers used by BMA software. It depends on the host_edma_drv driver. It will create a char device once loaded, offering interfaces (open, close, read, write and poll) to BMA to send/receive RESTful messages between BMC software. When the message is longer than 1KB, it will be cut into packets of 1KB. The other side, BMC's cdev_veth driver, will assemble these packets back into original mesages. Link: https://lkml.org/lkml/2020/6/22/752 Signed-off-by:
Naixin Yu <yunaixin@huawei.com>
Reviewed-by: Wang Qindong <wangqindong@huawei.com>
Acked-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> -
Naixin Yu authored
driver inclusion category: feature bugzilla: 34535 CVE: NA The BMA software is a system management software offered by Huawei. It supports the status monitoring, performance monitoring, and event monitoring of various components, including server CPUs, memory, hard disks, NICs, IB cards, PCIe cards, RAID controller cards, and optical modules. This host_veth_drv driver is one of the communication drivers used by BMA software. It depends on the host_edma_drv driver. The host_veth_drv driver will create a virtual net device "veth" once loaded. BMA software will use it to send/receive RESTful messages to/from BMC software. Link: https://lkml.org/lkml/2020/6/22/752 Signed-off-by:
Naixin Yu <yunaixin@huawei.com>
Reviewed-by: Wang Qindong <wangqindong@huawei.com>
Acked-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com>
-