Tags

v0.11.1

Fix various issues due to the changes of the 0.11.1
- Fix clock signals pulling through components (sub component to toplevel)
- Fix noRegisterAsLatch phases. Also this phase is applied to all none vital signals, even if that wasn't specified, to be more user friendly.
- Fix cases when a clock is defined as an component output but is also  used in the same component to drive registers
- Better autoconnect <>  implementation with better error reports

v0.11.0

This version radicaly change how SpinalHDL compiler work without changing the SpinalHDL syntax itself.

New feature :
- inout and Analog signals
- InOutWrapper tools allow to generate toplevels with their TriStates io bundles  converted into native inout tristates

Improvments :
- Better error reporting
- Better VHDL/Verilog generation

More safety :
- Signal assignements  over writing is now considerated as an error (can be bypassed via xxx.allowOverride
- Register without data assignement are nos considerated as an error (can by bypassed via xxx.allowUnsetRegToAvoidLatch

v0.10.14

v0.10.13
- Fix support of BigInt in 'is' statments
- Fix verilog shift bitwidth
- Better sensitivity list in VHDL and Verilog when switch statments are emited
- fromGray is now compatible with Verilator
- Better FMax for AXI4 interconnect libraries

Fix BaseType generics

v0.10.11 -> verilog improvments
Time and frequancy DSL now return dedicated class instead of BigInt
Verilog backend is Verilator ready
Verilog backend support comment attributes on signal
Verilog backend now use the = assignement operator in combinatorial always blocks
Verilog backend now generate much less intermediate nodes for Bool and Bits stuffs
Verilog backend case detection is improved
Better error messaging
Component PrePopTask is now recusivly flushed

v0.10.10
- Fix corner case emition of clock domains when clocks are provided by BlackBox
- Better hierarchy violation reporting
- Better Modifier toString
- Add ResetCtrl.asyncAssertSyncDeassert
- Add ClockDomain.local
- refractoring of ActiveKind into Polarity

v0.10.9
- Alow the usage of the SpinalHDL compiler repository without having git in the PATH
- Add checks on enumeration encodings to detect overlappings
- Better name managment for enumeration encodings
- Add functional enumeration encoding factory
- Misc refractoring
- Catch null pointers exception and display an user friendly error message
- Fix StreamFifoCC reset states
- Better UartCtrlRx timings
- Add support of CTS generation in UartCtrl driveFrom.read

v0.10.8
- SpinalTags could now tell if they their host node could be symplified
- Autoconnect(<>) operator is now able to connect sliced bitvectors
- Add header in generated files
- More ScalaDoc
- More feature for Counter and Timeout tools
- Time and hertz DSL now return dedicated object (HertzNumber, TimeNumber)
- Fix BlackBoxULogic

v0.10.7
- fix corner cases dontCareNodes generation in backends
- refractor signals.unused into signals.allowPruning
- fix bugs that forget to add some sensitivity list elements in corner cases

v0.10.6
Add UF/SF literals functions for fixed point
Add fixed bitwidth shift for Bits/UInt/SInt (|<<   |>>)
Add edge function in Bool
Fixedpoint now use BigDecimal in place of Double
Better error reporting
Replace asBits/asUInt/asSInt(something) by B/U/S(something)

- Add rotateLeft/rotateRight for Bits/UInt/SInt
- Add subdivideIn(x slices)
- Add subdivideIn(x bits)
- prePopTasks now remember the used clockdomain
- Now, switch cases that cover all cases doesn't need default case for combinatorial signals with no default

- Released jar can now be used on java 7
- Floating point implementation progress
- Add operator for BitWidth

v0.10.3
- Better error messaging
- Bitwise operators and Bits equals are now width strict
- Add Bits rotateLeft(Int)
- Fix out of range Bits static indexing error detection

Pinsec cleaning

v0.10.0

- IMasterSlave asMaster/asSlave now return nothing    Use master(xxx) slave(xxx)
- Data clone function now can return T <: Data in place of this.type
- Fix Iterable (Int) indexing
- Pinsec SoC

Mem enhancements

- Add optional automatic blackboxing of memories (see documentation)
- Mem refractoring
- Add user ways to add new transformation phases
- Mem now support mixed width ports
- Mem readWrite now support write mask

v0.9.2

- Adjustments in the aggregate assignement feature. Now for you can use the default feature only in assignements, and in this case, you can/have to omit the B/U/S prefix
Example :
myBits := (7 -> false, default -> true)
val myBits = B(7 -> false,(6 downto 0) -> true)
when(myBits === B(myBits.range -> true)) {...}
- Fix issue that prevented to instanciate Nodes outside the hierarchy

spinal.lib is now under MIT license
Add @@ interpreted concatenation
TriState is now part of spinal.lib.io package
Refractoring of some Stream utils before the documentation
Add APB3 compagnon object
Base type now implement directly base operator (:=,===,=/=,...) to avoid double implicit (Counter)
Add SystemVerilog keywords
Spinal core now print its version when started