Tags give the ability to mark specific points in history as being important
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v0.8.9
7b58a178 · ·FSM StateDelay now support UInt parameter When there is multiple reference of a io element, the io name win. Add Min/Max functions Update/Fix AXI4 Introduction of MentorDo Fix undeterministic io ordering which could change the generated code (wihtout modifing the beavorial) Compatibility with Verilog 1995 Vhdl compatibility of switch cases for Bits/UInt/SInt with restrictive tool like GHDL
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v0.8.7
d2d63981 · ·Fix AxiLiteR data width Prepare the field for new feature like automatic ModelSim .do generation to put signals in wave by a hierarchical manner
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v0.8.6
789aa6f8 · ·Remove some useless literal emition Divide by two the graph memory usage Fix register set as output with a randBoot
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v0.8.4
0a1e15f8 · ·Add enumeration encoding inferation phase Internal cleaning add FSM always{} blocks -
v0.8.3
dcc8846a · ·Fix verilog one hot enums Add name reservation for enumeration, which avoid name complicts
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v0.8.0
61b25047 · ·Verilog backend is now production ready Introduction of FSM syntax (spinal.lib.fsm)
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v0.7.5
b732b8f4 · ·Fix Verilog always blocks that use asyncronous signal as input data when a reset occure.
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v0.7.1
f61d0459 · ·Enum/Bits/UInt/SInt Switch statements are now emited by using VHDL cases in place of if statments
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