Tags

FSM StateDelay now support UInt parameter
When there is multiple reference of a io element, the io name win.
Add Min/Max functions
Update/Fix AXI4
Introduction of MentorDo
Fix undeterministic io ordering which could change the generated code (wihtout modifing the beavorial)
Compatibility with Verilog 1995
Vhdl compatibility of switch cases for Bits/UInt/SInt with restrictive tool like GHDL

AxiLite4SlaveFactory is now tested and ready to use.

Fix AxiLiteR data width
Prepare the field for new feature like automatic ModelSim .do generation to put signals in wave by a hierarchical manner

Remove some useless literal emition
Divide by two the graph memory usage
Fix register set as output with a randBoot

Fix unwanted emition when softReset is disable
Fix mem WriteOrRead node

Add enumeration encoding inferation phase
Internal cleaning
add FSM always{} blocks

Fix verilog one hot enums
Add name reservation for enumeration, which avoid name complicts

FSM : StateFsm refractoring of onDone to whenCompleted

FSM syntax adjustments

Verilog backend is now production ready
Introduction of FSM syntax (spinal.lib.fsm)

Fix Verilog always blocks that use asyncronous signal as input data when a reset occure.

Fix verilog memories that use byte enable
Fix VHDL signed resizes truncation

Verilog backend pass all regression test that the VHDL one is passing.

Verilog backend fixies
Enumeration encoding refractoring

Enum/Bits/UInt/SInt Switch statements are now emited by using VHDL cases in place of if statments

First release with Verilog backend (experimental, Enum cast missing)

Add missing printf

Better way to call Spinal
SpinalConfig

BusSlaveFactory is now syntactically stable

Fixed point is now stable
BusSlaveFactory introduction