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v1.3.0 is there !

This update improve SpinalSim by getting ride of the Scala continuation (which were providing the threading/corroutine @suspendable stuff) by replacing it with native JVM threads and adding a thread-less API for simulation speed sensitive things.

This doesn't break backward compatiblity and provide the following advantages :
- No more weird compilation errors related to Scala continuation
- You can now use all the scala syntax into you testbench (For instance for loop wasn't possible by the past inside suspendables)
- No more dependancies to Scala continuation (dying plugin ?)
- The thread-less API is even faster than scala continuation (clockDomain.onSampling{ ... }, ...)

The down sides are :
- The threaded API is now slower, count around 3 us for each thread resume + suspend
- use more memory as each simulation thread use a JVM thread

Also, the SpinalDoc is migrating to readTheDoc.

- Upgrade to sbt 1.2.7 and Scala 2.11.12.
- You can now use SpinalHDL and all the template projects with JDK >= 1.8
- Add simDeltaCycle access function + example
- SpinalSim Add forkSensitiveWhile primitive
- SpinalSim don't use anymore @suspendable stuff as now you can use regular scala for loop
- Add wishbone support with BusSlaveFactory, Arbiter, Decoder, Interconnect, Spi, Uart, ...
- add TriStateArray indexing (return Tristate(Bool))
- Implement ClockDomain.clockEnableDivisionRate (#166)
- Prohibit BusSlaveFactory to assign reads to the same bit more than once
- Rework SimManger to schedule calls instead of SimThreads
- Add Verilator 4.0 fst wave support (.withFstWave), not the default, can be slower than vcd file
- Add Ice40 blackbox into SpinalLib
- Improve StreamFifo for depth <= 1
- Add flush into Stream.m2sPipe
- SpinalSim UartDecoder now print messages on frame errors
- Implemented assertion that double-read on the same address is not possible (BusSlaveFactory).
- PipelinedMemoryBus interconnect now use raw setCompositeName
- Improve ClockDomain.simSpeedPrinter perf
- Add more composite naming inside the spinal.lib
- Add SpiXdrMasterCtrl with XIP support
- Allow Reg(Bool) init(Boolean)
- SpinalSim add thread-less primitives
- SpinalSim add rtl path option to include third party verilog IP into the verilog compilation
- Grap HexTools from VexRiscv
- fix Bits() with unconstrained bit width

v1.2.2

- Better nameables composition
- Add Ahb feature + fix issue wit AhbLite3ToApb3Bridge + verify overlaping for decoder
- Remove toAhbLite3Master function in AhbLite3
- Add a new option noAssert in SpinalConfig to disalbe all assert
- Add BRAM interface
- MuxOH with only two inputs optimisation
- Improve OHMasking combinatorial path
- Merge branch 'dev' of https://github.com/SpinalHDL/SpinalHDL into dev
- remove assert for SizeMapping + update DefaultAhbLite3Slave regarding to the spec
- (AhbLite3Decoder) Add the possibility to add a default slave
- Merge branch 'dev' of https://github.com/SpinalHDL/SpinalHDL into dev
- Fix bus when error occurs in AhbLite3ToApb3Bridge + Add remapAddress function to AhbLite3
- #137 Add past, changed, stable, rise, fall, initstate formal  statements
- Add muxListDc (don't care)
- Literals with poison values aren't anymore creating assignement overlap
- rework formal stuff #137
- Add CombInit
- Add >> << operators to AhbLite3
- Improve AhbLite3Decoder + add function toAhbLiteMaster2 to - AhbLite3
- Add >> << to AhbLite3
- Add noRandBoot feature

v1.2.1

- Add setAsReg / setAsComb / purify into Data class
- make is() require one parameter at least, syntactically
- Better Verilog switch case

v1.2.0 : HardType update

Instead of passing hardware datatype arguements as [T <: Data](dataType : T)  and then using cloneOf(dataType), please use [T <: Data](dataType : HardType[T]) and then dataType()

It is safer as it remove the usage of the cloneOf and also avoid instanciating a signal into the netlist just for generation purposes.

- Add anonymSignalUniqueness feature #144
- Literals are now propagated over one basetype
- Fix expression ScalaLocated trigger
- Better bit access error reporting
- Mem/Vec/Flow/Stream are now using HardType instead of cloneOf(signal)
- Hardtype don't instanciate stuff unless it's required
- missing unsetRegIfNoAssignementTag now emit a warning instead of a error
- Add parameter rtlHeader in SpinalConfig, use to generate a custom header in the rtl file generated
- Add bit vectors casting with specific width
- Add SpiDdr
- Add FlowMonitor
- Fix missing attribut postfix on ram
- Add a _ postfix in verilog on signals with duplicated names #133
- Fix non deterministic generation
- Add SpinalSystemVerilog (emit assertion in a SV way)
- Add extra flags option to verilator command
- Add `ifndef SYNTHESIS ... `endif around $display
- Typo enum encoding Sequancial -> Sequential
- fix #134 literal bit width
- verilog module's output which are internaly read doesn't generate an intermediat signal anymore
- Better Nameable priority control, add RegNext and Delay regs name
- fix Qsysify
- Fix Apb3Decoder lock on unmapped access
- fix mem blackboxing

v1.1.6
- ClockDomainTag can now be used to enforce clock domain checking on blackbox IO
- Fix Bug: resizeLeft() #123
- Fix prefix length for inlineRom (Verilog)
- Fix statemachine stateNext override
- Fix std_ulogic with blackbox
- Fix I2cCtrl

v0.11.6
- ClockDomainTag can now be used to enforce clock domain checking on blackbox IO
- Fix Bug: resizeLeft() #123
- Fix prefix length for inlineRom (Verilog)
- Fix statemachine stateNext override
- Fix std_ulogic with blackbox
- Fix I2cCtrl

v1.1.3

SpinalHDL :
- Verilog is now emiting ROM via the verilog memreadb macro
- You can keep the verilog inline rom via the inlineRom flag in SpinalConfig
- Workaround a VCS 2017 verilog shift issue

SpinalSim :
- add simulation phase API
- add SpinalSim retain/release feature
- Add experimental simulation tools for stream
- Add SimData

v1,1,2

- Fix uart decoder boot conditions
- Verilator now split files into chunks of 4000 lines to have a faster compilation on big designs
- Now the crossclocking check will also walk the clocks paths to see if two clock domains share the same common driver
- Add simPublic feature, which allow to read internal signals of the Dut during simulations
- MaskedLiteral are can no be compared to each other (usefull for hashmap)
- SwitchStatement elements are now able to properly give their code location
- Flip a direction less signal now produce a PendingError instead of a SpinalError  (Easier to debug)
- removing the need for `.` in `.elsewhen`(Thanks soronpo)
- SpinalSim run on Mac
- Fix assignement overriding detection
- SpinalSim add abstract randomize / assignBigInt

v1.1.1

- Fix SpinalSim simulation model (how it manage sensitivity, threads, backend evaluation, commands to write duts signals), this could break some of your testbench (clockdomain.waitUntilXX is now behaving exactly like the equivalent in VHDL/Verilog. In previous version, it was waiting one additional delta cycles)
- SpinalSim is now supported in windows
- Add SimTimeout
- Add Verilator model optimisation flag
- Catch Verilator flow exceptions
- Better clock crossing error reporting

v1.1.0

- Rework SimConfig API to allow building custom reusable configurations : SimConfig.withWave.compile(new Dut).doSim{ dut => }
- Refractoring of doManagedSim into doSim
- Add simSuccess, simfailure
- Add clockDomain.waitSampling
- Add clockDomain.forkSimSpeedPrinter
- Add doSimUntilVoid
- Fix sim waves and workspace naming collision checking
- Fix sim workspace colision detection
- Verilator compile with -j2 now

v1.0.5

- *You need to add fork := true into your build.sbt if you want to run tests from sbt command lines*
- Now simulation files are emited in the simWorkspace folder by default
- You can override the simWorkspace path by setting the SPINALSIM_WORKSPACE environement variable
- Clean the why how simulations files are organized
- add sim signal.randomize()
- Now the VHDL and Verilog backend split long expressions on a multiple assignement. (max 32 expressions per assignement)
- Sim waitUntilRisingEdge(count = 100)
- SpinalConfig(verbose = true) to print phase timings
- Add sim ClockDomain.waitActiveEdgeWhere(cond)
- VerilatorBackend now use JNI instread of JNR-FFI to remove a memory leak (it also reduce jar dependancies)
- Reduce emited symboles from the Verilator shared object (fix crash when running multiple test from different hardware durring a single VM execution)
- SpinalSim is now ready to run multiples tests in multiple threads with multiples  hardwares at the same time
- Sim API fix toInt (now will return a Int instead than a Long)

v1.0.4

- Now you can create a new clock domain during the simulation by pointing corresponding toplevel inputs
- Add verilator compilation start message
- Better verilator sim faild message
- Fix sim ClockDomain.forkStimulus async reset

v1.0.3

- Add sim JtagTcp, UartEncoder, UartDecoder
- Improve memory usage, performance and scaling of design's errors reporting
- Fix verilator backend string imports
- Fix I2C controller interrupt x-prop

v1.0.2

- Add simExit()
- Add enum read/write support in sim
- Add sim seed
- Add sim wave depth
- Fix anonymous component naming
- Rework sim api includes
- Add sim ClockDomain stimulus generation utiles

v1.0.1

- Fix sim zerowidth io
- Fix sim clockdomain access

v1.0.0

- Add simulation capabilities via Verilator and an abstract API

v0.11.5

- Fix latch/unasigned signals for components inputs
- If no memory blackboxer is specified in the SpinalConfig, then the default one is added with "on request" policy
- Fix ResetArea

v0.11.4

- Add BitVector.resize(8 bits) syntax
- Remove BitVector.apply(Int,Int) in favor of BitVector.apply(Int downto Int)
- Vec.apply(UInt) is now emited with dedicated process + switch statement by backends instead of a 2->1 mux tree
- Verilog backend now use always@(*) instead of always@(a,b,c, ...)
- Rework BusSlaveFactory to allow multicycle registers access and to map memories
- restore onlyStdLogicVectorAtTopLevelIo feature
- Fix Vec(Vec(in/out/master/slave/Reg(x)))
- Others lib fixes

v0.11.3

- Now backends will automaticaly merge combinatorial process if they share some conditional scope
- Add xx.noBackendCombMerge feature to avoid the above feature on a specific signal
- BusSlaveFactory rework primitives to allow ranged access and bus halt request for multicycles registers
- remove automatic keywords from functions emited into the verilog backend
- Fix default feature when used on outputs
- More AXI4 fancy convertions functions
- Add noBackendCombMerge feature
- Add noCombLoopCheck syntax
- addGeneric syntax added for blackboxes
- Fix axi driveAx region default value
- Better quartus/vivado flow

v0.11.2

Allow to keep undrived all non-design-vital register